W681308DG [NUVOTEM TALEMA]
W681308 USB Audio Controller from Nuvoton integrates fast 8051 Microcontroller Unit (MCU); W681308 USB音频控制器由新唐集成了高速8051微控制器单元（MCU ）
| 型号： | W681308DG |
| 厂家： | 
NUVOTEM TALEMA |
| 描述： | W681308 USB Audio Controller from Nuvoton integrates fast 8051 Microcontroller Unit (MCU) |
| 文件： | 总64页 (文件大小：981K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W681308
W681308
USB AUDIO CONTROLLER
Data Sheet
Revision 1.2
W681308
TABLE OF CONTENT
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ............................................................................................................................................... 6
FEATURES....................................................................................................................................................................... 6
PIN CONFIGURATION..................................................................................................................................................... 8
PIN DESCRIPTION .......................................................................................................................................................... 9
BLOCK DIAGRAM.......................................................................................................................................................... 11
MEMORY MAP............................................................................................................................................................... 12
6.1
6.2
PROGRAM MEMORY MAP ........................................................................................................................................... 12
DATA MEMORY MAP .................................................................................................................................................. 12
7.
REGISTERS................................................................................................................................................................... 13
7.1
MCU CLOCK RATE SELECT REGISTER ....................................................................................................................... 13
INTERRUPT CONTROL REGISTERS .............................................................................................................................. 13
KEYPAD IO, LCD, UART AND GPIO CONTROL REGISTERS ......................................................................................... 13
GAIN STAGE AND MIXER CONTROL REGISTERS............................................................................................................ 14
PCM CONTROL REGISTERS....................................................................................................................................... 14
CODEC CONTROL REGISTERS.................................................................................................................................. 14
SPI CONTROL REGISTERS......................................................................................................................................... 15
W2S CONTROL REGISTERS....................................................................................................................................... 15
RING TONE (PWM) CONTROL REGISTERS .................................................................................................................. 16
FULL/HALF DUPLEX ACOUSTIC ECHO CANCELLATION (AEC) CONTROL REGISTERS ........................................................ 16
USB CONTROLLER REGISTERS.................................................................................................................................. 18
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
8.
MICROCONTROLLER ................................................................................................................................................... 21
8.1
8.2
FEATURES................................................................................................................................................................ 21
MEMORY ORGANIZATION ........................................................................................................................................... 21
8.2.1 Program Memory............................................................................................................................................... 21
8.2.2 Data Memory..................................................................................................................................................... 21
8.2.3 Special Function Registers (SFR) ..................................................................................................................... 22
8.3
8.4
POWER MANAGEMENT............................................................................................................................................... 22
RESET CONDITIONS .................................................................................................................................................. 23
8.4.1 External Reset................................................................................................................................................... 23
8.4.2 Watchdog Reset................................................................................................................................................ 23
8.5
8.6
INTERRUPTS............................................................................................................................................................. 23
PROGRAMMING TIMERS AND COUNTERS ..................................................................................................................... 24
8.6.1 Timers/Counters 0 and 1 ................................................................................................................................... 24
8.6.2 Timer/Counter 2................................................................................................................................................. 25
2
Rev1.2
W681308
8.6.3 Watchdog Timer ................................................................................................................................................ 25
8.7
8.8
SERIAL PORT (UART)............................................................................................................................................... 28
OTP ROM .............................................................................................................................................................. 28
9.
CLOCK CONTROL AND RESET ................................................................................................................................... 29
9.1
CLOCK CONTROL...................................................................................................................................................... 29
9.1.1 Overview............................................................................................................................................................ 29
9.1.2 Clock Generation............................................................................................................................................... 29
9.1.3 Control Register................................................................................................................................................. 30
INTERRUPT CONTROL ............................................................................................................................................ 31
10.
10.1
10.2
10.3
11.
OVERVIEW ............................................................................................................................................................... 31
FUNCTIONALITY ........................................................................................................................................................ 31
INTERRUPT CONTROL REGISTERS .............................................................................................................................. 32
INTERFACE LOGIC................................................................................................................................................... 33
SOFTWARE KEYPAD SCANNER ................................................................................................................................... 33
GPIO S ................................................................................................................................................................... 34
LCD CONTROL......................................................................................................................................................... 35
UART I/O CONTROL................................................................................................................................................. 35
PCM INTERFACE , GAIN STAGE AND MIXER ........................................................................................................ 36
PCM INTERFACE ...................................................................................................................................................... 36
GAIN STAGE ............................................................................................................................................................. 36
MIXER ..................................................................................................................................................................... 37
CONNECTION CASE EXAMPLE .................................................................................................................................... 37
MIXER CASE EXAMPLES WITH REGISTER SETTING ....................................................................................................... 39
I2S REGISTER SETTING EXAMPLE .............................................................................................................................. 42
AUDIO CODEC INTERFACE..................................................................................................................................... 43
OVERVIEW ............................................................................................................................................................... 43
AUDIO CODEC SIGNAL PATH.................................................................................................................................... 43
MICROPHONE INTERFACE AND AUXILIARY INTERFACE ................................................................................................... 44
SERIAL PERIPHERAL INTERFACE.......................................................................................................................... 47
OVERVIEW ............................................................................................................................................................... 47
DATA AND SIGNAL FORMAT OF SPI............................................................................................................................ 47
FSM OF SPI ............................................................................................................................................................ 47
FIFO AND RAM OF SPI ............................................................................................................................................ 48
INTERRUPT SOURCES................................................................................................................................................ 48
NUVOTON 2-WIRE SERIAL BUS.............................................................................................................................. 49
11.1
11.2
11.3
11.4
12.
12.1
12.2
12.3
12.4
12.5
12.6
13.
13.1
13.2
13.3
14.
14.1
14.2
14.3
14.4
14.5
15.
3
Rev1.2
W681308
15.1
16.
OVERVIEW ............................................................................................................................................................... 49
ICE FUNCTION BY JTAG STD. IEEE 1149.1............................................................................................................ 49
OVERVIEW ............................................................................................................................................................... 49
SCAN CHAINS AND JTAG INTERFACE.......................................................................................................................... 49
PIN DESCRIPTION ..................................................................................................................................................... 49
RESET BEHAVIOR ..................................................................................................................................................... 50
RING TONE (PWM) GENERATOR............................................................................................................................ 50
OVERVIEW ............................................................................................................................................................... 50
FULL/HALF DUPLEX ACOUSTIC ECHO CANCELLATION(AEC) ............................................................................ 51
FUNCTION CONTROL REGISTERS................................................................................................................................ 51
USB DEVICE CONTROLLER AND TRANSCEIVER ................................................................................................. 52
OVERVIEW ............................................................................................................................................................... 52
FUNCTIONAL DESCRIPTION ........................................................................................................................................ 52
16.1
16.2
16.3
16.4
17.
17.1
18.
18.1
19.
19.1
19.2
19.2.1
19.2.2
Endpoints ...................................................................................................................................................... 53
Descriptor RAM............................................................................................................................................. 54
20.
ELECTRICAL CHARACTERISTICS .......................................................................................................................... 55
ABSOLUTE MAXIMUM RATINGS................................................................................................................................... 55
RECOMMENDED OPERATING CONDITIONS ................................................................................................................... 55
DC CHARACTERISTICS .............................................................................................................................................. 56
ANALOG TRANSMISSION CHARACTERISTICS................................................................................................................. 56
ANALOG DISTORTION AND NOISE PARAMETERS ........................................................................................................... 57
20.1
20.2
20.3
20.4
20.5
20.5.1
20.5.2
20.5.3
8kHz sampling............................................................................................................................................... 57
16kHz sampling............................................................................................................................................. 57
48kHz sampling............................................................................................................................................. 58
20.6
20.7
20.8
PROGRAMMABLE OUTPUT LINEAR REGULATOR............................................................................................................ 58
USB PHY ELECTRONIC CHARACTERISTICS ( 25°C, DVDD= 3.3V, VDDL =1.8V) ......................................................... 59
USB PLL ELECTRONIC CHARACTERISTICS.................................................................................................................. 60
TYPICAL APPLICATION REFERENCE CIRCUIT ..................................................................................................... 61
USB VOIP SPEAKER PHONE APPLICATION ................................................................................................................... 61
PACKAGE DIMENSIONS .......................................................................................................................................... 62
ORDERING INFORMATION...................................................................................................................................... 63
REVISION HISTORY ................................................................................................................................................. 64
21.
21.1
22.
23.
24.
4
Rev1.2
W681308
LIST OF TABLES
Table 1 Pin Description .......................................................................................................................................................... 10
Table 2 W681308 MCU SFR location..................................................................................................................................... 22
Table 3 Interrupt Priority Structure.......................................................................................................................................... 23
Table 4 Timer Mode/Control TMOD/TCON SFR .................................................................................................................... 24
Table 5 Timer 2 Mode/Control TMOD/TCON SFR ................................................................................................................. 25
Table 6 Time-Out Values For Watchdog Timer...................................................................................................................... 26
Table 7 Watchdog Control WDCON SFR............................................................................................................................... 26
Table 8 Watchdog Control Bits............................................................................................................................................... 27
Table 9 Watchdog Timer Timeout Control.............................................................................................................................. 27
Table 10 Serial Control SCON SFR ....................................................................................................................................... 28
Table 11 JTAG Pin Description .............................................................................................................................................. 49
Table 12 W681308 USB Endpoint Definitions........................................................................................................................ 53
Table 13 USB Descriptor RAM Definitions ............................................................................................................................. 54
LIST OF FIGURES
Figure 1 Pin diagram ................................................................................................................................................................ 8
Figure 2 W681308 Function Block Diagram........................................................................................................................... 11
Figure 3 Interrupt Structure .................................................................................................................................................... 31
Figure 4 Keypad Scanning Application Circuit........................................................................................................................ 33
Figure 5 PCM Interface, Gain Stage and Mixer Location ....................................................................................................... 36
Figure 6 Mixer Connection Case Examples ........................................................................................................................... 37
Figure 7 Mixer Examples with Registers Setting .................................................................................................................... 39
Figure 8 W681308 CODEC Signal Path Control .................................................................................................................... 43
Figure 9 Microphone Voltage Gain Mode............................................................................................................................... 45
Figure 10 Microphone Current Gain Mode ............................................................................................................................. 45
Figure 11 Microphone Auxiliary Input Mode ........................................................................................................................... 46
Figure 12 SPI Block Diagram ................................................................................................................................................. 47
Figure 13 Ring Tone Generator Block.................................................................................................................................... 50
Figure 14 Signal flow through Acoustic Echo Cancellation in the speech processor.............................................................. 51
Figure 15 USB Function Block Diagram................................................................................................................................. 52
Figure 16 W681308 Reference Design Application Circuit..................................................................................................... 61
5
Rev1.2
W681308
1.
General Description
W681308 USB Audio Controller from Nuvoton integrates fast 8051 Microcontroller Unit (MCU), Universal Serial Bus (USB)
2.0 Full Speed compliant controller with PHY, 16bit high quality Analog to Digital Converter / Digital to Analog Converter
(ADC/DAC) with 8/16/48 KHz wide band sampling rates, speaker phone and echo cancellation, 8 KB One Time
Programmable (OTP) program memory and 1 KB data memory in a single 48 pin Low-profile Quad Flat Package (LQFP).
MCU includes Joint Test Access Group (JTAG) In-Circuit Emulation(ICE) interface and can handle customer programs such
as keypad scan, LCD control, caller list download, and USB and CODEC control among other features. W681308 provides
highest integration and low BOM cost solution with 8051-based development platform for USB Audio peripherals and USB
VoIP devices such as Skype® , other IM and SIP-based application.
With Nuvoton’s market proven CODEC product experience, W681308 is designed to provide high audio quality in VoIP and
audio devices applications and deliver USB Audio/VoIP solution with the shortest time to market, time to volume and time to
profit
2.
Features
8 Bit Turbo MCU
Embedded 12/24/48 MHz Turbo 8051 MCU with 4 Clocks per machine Cycle
1 KB system RAM, 8 KB OTP ROM
256 byte internal RAM (8051)
Power on Reset circuit
Software Idle mode
In Circuit Emulation (ICE) through JTAG Interface
High Quality 16 bit Mono Audio Linear CODEC
Built-in 8/16/48 KHz sampling rate wideband mono audio CODEC and true 16-bit resolution ADC/DAC with internal 24-bit audio
processing for both record and playback
Analog microphone(MIC) amplifier and speaker driver with internal programmable gain stage
82 dB Receive SNR @ 8 Ohm load
USB 2.0 Full speed (FS) Interface with integrated PHY
USB 2.0 FS compliant device controller and PHY with 12 Mbps communication speed
Support 6 USB endpoints configuration: Control, ISO IN/OUT, Bulk IN/OUT and Interrupt IN
512-Byte RAM-based USB descriptor for multiple USB device support through 8051 MCU
Less than 500uA supply current in suspend mode
Fully integrated cap-less microphone amplifier with microphone bias
Dual earphone / speaker driver and buzzer
Integrated DAC switch for earphone or speaker phone
Integrated Acoustic Echo Cancellation (AEC)
Support both half-duplex AEC and 32ms full duplex AEC
Built-in digital Auto Gain Control (AGC) with microphone input for speaker phone application
Integrated keypad control pins and GPIO
Suitable for VoIP application
Volume up and down
Dial / hang up
Microphone and speaker phone mute
LED indicators
6
Rev1.2
W681308
Number pad control
User programmable keys
Keypad scanning
LCD Module interface control
UART
Programmable UART port for serial data application
PCM Interface
Master linear PCM interface to external PCM device such as Nuvoton’s ProX CODEC/SLIC
SPI interface
Works in master mode to control Liquid Crystal Display (LCD) Module or other SPI slave devices
Support Winbond serial flash device with SPI interface
W2S 2 Wire interface
Support 2 wire interface for EEPROM three format page modes
USB 5V voltage supply
Built-in linear regulator on chip supports 3.3V to 1.8V conversion for digital core power
USB 5V to 3.3V supply power using external transistors
Package
48-pin LQFP package 7mmx7mmx1mm
Application
USB audio peripheral box/ USB sound card
USB microphone / USB mono headset
Wired and Wireless USB VoIP phone with LCD
USB VoIP ATA and Gateway
PSTN and USB VoIP dual phone
General USB MCU and audio application
7
Rev1.2
W681308
3.
Pin Configuration
36
35
34
33
32
31
30
29
28
27
26
25
VREF1
VREF2
MCP
1
2
GPIO14/UARTT(nTRST)
GPIO13/UARTR(TMS)
3
DGND
MCO
4
XTALO
XTALI
W681308
48 Pin
LQFP
RGND
5
6
VDDL
DVDD
AGND
SPP
7
DN
DP
EARP
8
9
AVDD
EARN
SPN
DGND
10
11
12
GPIO3/LED
GPIO0(TCK)
AGND
Figure 1 Pin diagram
8
Rev1.2
W681308
4.
Pin Description
Please refer to Design Guide for product design details.
Driver
Pin
No
State in
Reset
Pin Name
Functionality
Pin Type
Strength
UARTT
/nTRST
/GPIO 14
UART TX data / JTAG TAP controller reset input
/GPIO 14
1
2
Pull-H
Pull-H
D
D
I/O
2 mA
UARTR
/TMS
UART Rx data / JTAG TMS input / GPIO 13
I/O
2 mA
/GPIO 13
DGND
XTALO
XTALI
3
4
Digital ground supply voltage
Crystal clock output
D
A
A
D
D
A
A
D
D
D
P
O
—
—
5
Crystal clock input
I
—
VDDL
6
Logic supply voltage
P
—
DVDD
7
Digital supply voltage
P
—
DN
8
USB D- connection
I/O
I/O
P
—
DP
9
USB D+ connection
—
DGND
10
11
12
Digital ground supply voltage
LED connection / GPIO 3
JTAG Clock with internal pull up / GPIO 0
—
LED/GPIO 3
TCK/GPIO 0
Pull-H
Pull-H
I/O
I/O
16 mA
16 mA
Chip select (used for SPI flash or normal SPI) /GPIO
11
CS/GPIO 11
13
14
Pull-H
Pull-L
D
D
I/O
I/O
2 mA
2 mA
Serial port bit clock ( For SPI flash or normal SPI)
/GPIO 10
SCLK/GPIO 10
SDI/GPIO 9
SDO/GPIO 8
CSL/GPIO 12
FS/GPIO 7
15
16
17
18
19
20
21
22
Pull-L
Pull-H
Pull-H
Pull-L
Pull-L
Pull-L
Pull-L
Pull-H
Serial port data in (SPI flash/ SPI) /GPIO 9
Serial port data out (SPI flash/ SPI) /GPIO 8
LCD, LCM chip select /GPIO 12
D
D
D
D
D
D
D
D
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2 mA
2 mA
2 mA
2 mA
2 mA
2 mA
2 mA
2 mA
PCM Frame Sync output /GPIO 7
PCM Bit Clock output or input / GPIO 6
Serial PCM Receive data input / GPIO 4
Serial PCM Transmit data output / GPIO 5
JTAG Data Input / GPIO 1
BCLK/GPIO 6
PCMR/GPIO 4
PCMT/GPIO 5
TDI/GPIO 1
9
Rev1.2
W681308
Driver
Pin
No
State in
Reset
Pin Name
Functionality
JTAG Data Output / GPIO 2
Pin Type
Strength
TDO/GPIO 2
VPP
23
24
Pull-L
D
A
I/O
2 mA
Reset signal for digital core. Tie this pin to 6.75V for
programming the OTP ROM
P
—
AGND
SPN
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Analog ground supply voltage
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
P
O
—
—
Speaker1 negative connection
Speaker2 negative connection
Analog supply voltage
EARN
O
—
AVDD
P
—
EARP
Speaker2 positive connection
O
—
SPP
Speaker1 positive connection
O
—
AGND
Analog ground supply voltage
P
—
RGND
Low noise ADC and DAC reference
The microphone amplifier output
Microphone positive connection
Voltage reference
P
—
MCO
G
—
MCP
O
—
VREF2
O
—
VREF1
Voltage reference
O
—
REGL
Linear regulator base control output
Keypad row Y4 connection /GPIO 24
Keypad row Y3 connection /GPIO 23
Keypad row Y2 connection /GPIO 22
Keypad row Y1 connection /GPIO 21
Keypad row Y0 connection /GPIO 20
Keypad column X4 connection /GPIO 19
Keypad column X3 connection /GPIO 18
Keypad column X2 connection /GPIO 17
Keypad column X1 connection /GPIO 16
Keypad column X0 connection /GPIO 15
O
—
KY4/GPIO 24
KY3/GPIO 23
KY2/GPIO 22
KY1/GPIO 21
KY0/GPIO 20
KX4/GPIO 19
KX3/GPIO 18
KX2/GPIO 17
KX1/GPIO 16
KX0/GPIO 15
Pull-H
Pull-H
Pull-H
Pull-H
Pull-H
Pull-L
Pull-L
Pull-L
Pull-L
Pull-L
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2 mA
2 mA
2 mA
2 mA
2 mA
2 mA
2 mA
2 mA
2 mA
2 mA
Tie to DGND for normal operation. Tie to DVDD to
enable JTAG function.
JTAG
48
Pull-L
D
I
2 mA
Table 1 Pin Description
NOTE: All GPIO pins modes are controlled by register settings.
10
Rev1.2
W681308
5.
Block Diagram
Figure 2 W681308 Function Block Diagram
There are 4 major function block groups in the USB Audio Controller:
Turbo 8051 MCU, registers, OTP/RAM memory and peripheral ports
16-bit audio quality CODEC with AEC/AGC
USB 2.0 FS interface with SIE, Full Speed PHY and 6 end points
SPI / UART / I2C / PCM / I2S and GPIO interfaces.
11
Rev1.2
W681308
6.
Memory Map
6.1
Program Memory map
Memory is mapped into program memory and data memory. Program memory is mapped from 0x0000 to 0x1FFF (8 KB), it
is used by internal OTP.
6.2
Data Memory map
Size (Byte)
Data memory address
Function
Total
Available
4
0x1440 ~ 0x1443
0x144A ~ 0x145F
0x1460 ~ 0x146F
0x1470 ~ 0x1474
0x1480 ~ 0x148A
0x14A0 ~ 0x14AF
0x14B0 ~ 0x14BA
0x14C0 ~ 0x14C5
0x1600 ~ 0x167F
0x1680 ~ 0x16FF
0x1800 ~ 0x19FF
0x2000 ~ 0x23FF
0x2800 ~ 0x2FFF
0x3000 ~ 0x33FF
4
22
Interrupt Control Registers
20
16
Keypad IO, LCD, UART and GPIO Control Registers
Gain stage and Mixer Control Registers
PCM Control Registers
16
16
5
16
11
CODEC Control Registers
16
15
SPI Control Registers
16
11
W2S Control Registers
16
5
Ring Tone(PWM) Control Registers
Full/Half Duplex AEC Control Registers
AGC Control Registers
128
128
512
1024
2048
1024
120
16
57
USB Control Registers
1024
2048
1024
USB RAM Based Descriptor Field
Full Duplex AEC RAM
System RAM
12
Rev1.2
W681308
7.
The registers are mapped by function.
7.1 MCU Clock Rate Select Register
Registers
Value At
Function
Reset
Address
0x1440
Name
Mode
R/W
MCU Rate Select
0x00
MCU system clock rate selection
7.2
Interrupt Control Registers
Value At
Reset
Address
0x1441
Name
Mode
Function
Interrupt Source
Interrupt Enable
Interrupt Priority
R/W
R/W
R/W
0x00
0x00
0x00
Enable / Disable Interrupt source
Enable / Disable Interrupt function
Set Interrupt priority
0x1442
0x1443
7.3
Keypad IO, LCD, UART and GPIO Control Registers
Value At
Reset
Address
Name
Mode
R/W
Function
0x144A~
0x144B
GPIO [14:0] Pull
Up/Down Control
0x00
Enable/Disable GPIO [14:0] Pull Up/Down
Keypad I/O (GPIO
[24:15]) and GPIO
[14:0] Pull Up/Down
Selection
0x144C~
0x144F
Select Pull Up/Down for Keypad I/O (GPIO [24:15]) and
GPIO [14:0]
R/W
0x00
Keypad I/O(GPIO
[24:15]) and GPIO
[14:0] Status
0x1450~
0x1453
Indicate Keypad I/O(GPIO [24:15]) and GPIO [14:0] pin
status
R/W
R/W
0x00
0x00
Keypad I/O(GPIO
[24:15]) and GPIO
[14:0 Direction Control
0x1454~
0x1457
Select Keypad I/O(GPIO [24:15]) and GPIO [14:0]
Input/Output Direction
Keypad I/O(GPIO
[24:15]) and GPIO
[14:0] Interrupt control
0x1458~
0x145B
Enable/Disable Keypad I/O(GPIO [24:15]) and GPIO
[14:0] Interrupt
R/W
0x00
Enable/Disable LCD data, clock and chip selection
control.
0x145E
0x145F
LCD Control
R/W
R/W
0x00
0x00
UART I/O Control
Enable/Disable UART I/O control.
13
Rev1.2
W681308
7.4
Gain Stage and Mixer Control Registers
Value At
Function
Reset
Address
Name
Mode
Enable/Disable Gain Stage for Side tone Gain, CODEC
Gain Stage and Mixer
Control
to AEC Gain, AEC to CODEC Gain, AEC to Mixer Gain,
Mixer to AEC Gain and USB in/USB out Gain. Select
0x1460
R/W
0x00
Mixer mode for USB, CODEC and PCM.
Set Audio Gain Index Register Value (Side tone Gain,
0x1461~
0x1467
CODEC to AEC Gain, AEC to CODEC Gain, AEC to
Mixer Gain, Mixer to AEC Gain, USB in and USB out
Gain Stage Index
R/W
0x00
Gain)
0x1468~
0x146B
0x146C~
0x146F
MCU Record
MCU Play
R
0x00
0x00
Enable/Disable MCU to monitor USB ISO In/Out data
Enable/Disable MCU write data to USB and CODEC
R/W
7.5
PCM Control Registers
Name
Value At
Reset
Address
Mode
R/W
R/W
Function
Enable/Disable PCM Interface and Bit Clock / Frame
Sync selection
0x1470
0x1472
PCM Control
0x00
0x00
PCM Frame Sync
Length
Set Frame Sync pulse length
7.6
CODEC Control Registers
Value At
Reset
Address
0x1480
0x1481
Name
CODEC control
Dither Control
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Enable/Disable CODEC, Select Sampling Rate and
High Pass Frequency
0x00
0x00
Enable/Disable Dither Function
0x1482~
0x1483
0x1484~
0x1485
CODEC ADC Digital
Gain
CODEC DAC Digital
Gain
0x04 0x00
Set Digital ADC Path Gain
0x04
0x00
Set Digital DAC Path Gain
0x1488
0x1489
CODEC MIC Control
CODEC MIC Control
0x00
0x00
0x00
0x00
Set microphone bias voltage and bias resistor reference
Select MIC interface mode and Set microphone gain
CODEC Speaker
Control
CODEC Analog
Control
Attenuate speaker phone/ earphone speaker and Set
speaker gain
0x148A
0x148B
Enable/Disable CODEC Analog Block
14
Rev1.2
W681308
7.7
SPI Control Registers
Value At
Function
Reset
Address
0x14A0
Name
Clock
Interface
Command
Interface Control
Mode
R/W
R/W
RW
R/W
RW
RW
RW
R
SPI
and
Enable/Disable SPI interface and Select SPI bit clock
rate
0x00
SPI
Set SPI interface command length, R/W and other
control
0x14A1
0x14A2
0x14A3
0x00
SPI Data Length
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Set SPI interface data field length
SPI Interrupt Control
Enable/Disable SPI interface interrupt
Set SPI interface command byte 1 to 5
Set SPI interface clock format
0x14A4~
0x14A8
SPI Command Byte
Control
SPI Clock Format
Control
0x14AB
0x14AC
0x14AD
0x14AE
0x14AF
SPI FIFO Data
SPI Byte Count
SPI Write Count
SPI Read Count
Read/write data from SPI interface FIFO
Current SPI interface FIFO counter value
MCU current Write point for SPI interface FIFO
MCU current Read point for SPI interface FIFO
R/W
R/W
7.8
W2S Control Registers
Value At
Reset
Address
Name
W2S Enable
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
0x14B0
0x14B1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Enable/Disable W2S bus controller
Set different page mode and page size of EEPROM
Set W2S bit clock rate
EEPROM control
0x14B2~
0x14B3
W2S Clock
0x14B4
0x14B5
0x14B6
0x14B7
0x14B8
0x14B9
0x14BA
W2S R/W FIFO
Read/Write W2S compatible device
Set W2S Read/Write and FIFO control
Indicate W2S FIFO space and ACK signal status
Indicate W2S FIFO read pointer
Indicate W2S FIFO write pointer
W2S R/W Operation
Control
W2S Status
FIFO Read Pointer
FIFO Write Pointer
ACK Failure Detect
Set ACK failure detect and indicate failure data pointer
in FIFO
Indicate status for SCL_in, finite state machine state
and interrupt signal status
W2S
Miscellaneous
Control
15
Rev1.2
W681308
7.9
Ring Tone (PWM) Control Registers
Value At
Function
Reset
Address
Name
PWM Clock
Mode
R/W
R/W
R/W
R/W
R/W
0x14C0
0x14C2
0x14C3
0x14C4
0x14C5
0x00
0x00
0x00
0x00
0x00
Enable/Disable PWM Operation Clock
Set Tone 1 Volume
PWM Tone1 Control
PWM Tone1
Frequency
Set Tone 1 Frequency
Set Tone 2 Volume
PWM Tone2 Control
PWM Tone2
Frequency
Set Tone 2 Frequency
7.10
Full/Half Duplex Acoustic Echo Cancellation (AEC) Control Registers
Value At
Reset
Address
0x1600
0x1601
0x1602
Name
Mode
R/W
R/W
R/W
Function
AEC Configuration
AEC Reset Control
AEC Mode Control
0x96
Set AEC Configuration parameters
Set AEC power down and reset function
Set AEC Full/Half duplex mode and Noise suppressor
0x08
0x03
Double Talk Long
Term Power Time
Constant
Double Talk Short
Term Power Time
Constant
Set time constant for long term power estimation of
double talk
0x1605
0x1606
R/W
R/W
0x09
0x0B
Set time constant for short term power estimation of
double talk
0x1607~
0x1608
0x1609~
0x160A
Double Talk Hangover
Time
Double Talk Deviation
Threshold
Set hangover time window of double talk detection
algorithm
R/W
R/W
0x0020
0x19A8
Set deviation power threshold of double talk
Double Talk Long
Term Power
Threshold
0x160B~
0x161C
Set power threshold for long term power estimation of
double talk
R/W
0x0000
Double Talk Short
Term Power
Threshold
AEC Divergence
Threshold
Voice Detect Long
Term Power Time
Constant
0X160D~
0x160E
Set power threshold for short term power estimation of
double talk
R/W
R
0x1010
0x0F
0X160F
0x1610
Set AEC Divergence threshold
Set time constant for long term power estimation of
Voice Detect
R/W
0x09
Voice Detect Short
Term Power Time
Constant
Voice Detect
Hangover Time
Set time constant for short term power estimation of
Voice Detect
0x1611
R/W
R/W
0x0B
0x1612~
0x1613
Set hangover time window of Voice Detect detection
algorithm
0x0009
16
Rev1.2
W681308
Value At
Function
Reset
Address
Name
Mode
R/W
0x1614~
0x1615
Voice Detect Deviation
Threshold
0x1998
Set deviation power threshold of Voice Detect
Voice Detect Long
Term Power
Threshold
Voice Detect Short
Term Power Low
Threshold
Voice Detect Short
Term Power High
Threshold
0x1616~
0x1617
Set power threshold for long term power estimation of
Voice Detect
R/W
R/W
R/W
R/W
0x1998
0x1618~
0x1619
Set
Low power threshold for short term power
0x0BA8
0x1038
0x0000
estimation of Voice Detect
0X161A~
0X161B
Set
high power threshold for short term power
estimation of Voice Detect
Voice Detect Short
Term Power Average
Threshold
0X161C~
0X161D
Set average power threshold for short term power
estimation of Voice Detect
0X161E~
0X161F
0x1620~
0x1621
0x1622~
0x1623
Power Cut Off Control
AGC Threshold
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x1998
0x2000
0x0320
0x02
Set zero reference bias for power cut off estimation
Set maximum output power of AGC
AGC Noise Threshold
AGC Gain from AEC
Set AGC calculated input power with time constant
Set maximum gain for post echo cancellation signal
Set delay time constant for long term gain estimation
Set delay time constant for short term gain estimation
Enable/Disable soft clip(SC) function
0x1624
0x1625
0x1626
0x1628
0x1629
0x162A
AGC Gain Time
constant
AGC Gain Time
constant
0xBB
0x09
Soft Clip Control
0x00
Soft Clip Normal Gain
Index
Soft Clip Low Gain
Index
Set gain index of voice detect for soft clip module at
normal gain mode
Set gain index of voice detect for soft clip module at low
gain mode
0x00
0x00
0x162B~
0x162C
Soft Clip Threshold
0x1000
0x07
Set threshold level to select soft clip gain mode
Soft Clip Power Time
Constant
Soft Clip Gain Time
Constant
Acoustic Suppression
1 Time Constant
Acoustic Suppression
1 attenuation
Acoustic Suppression
2 Time Constant
Acoustic Suppression
2 attenuation
Noise Suppressor
Control
Noise Suppressor
Set time constant for short term power calculation of
voice detect soft clip
Set time constant to smooth gain mode change of soft
clip
Set time constant of acoustic suppression (AS1) for
convergence towards target
Set maximum attenuation value for acoustic
suppression (AS1) algorithm
Set time constant of acoustic suppression (AS2) for
convergence towards target
Set maximum attenuation value for acoustic
suppression (AS2) algorithm
Set noise suppressor gain index and short term power
time constant
Set time constant for rise and fall of noise suppressor
gain index
0x162D
0x162E
0x1630
0x07
0x77
0x1631-
0x1632
0x1CA8
0x77
0x1633
0x1634~
0x1635
0x1CA8
0xBB
0xBB
0x1638
0x1639
Gain Time Constant
17
Rev1.2
W681308
Value At
Function
Reset
Address
Name
Mode
R/W
Noise Suppressor
Active Power
Threshold
0x163A~
0X163B
0x03E8
Set threshold level for active noise suppressor
0x1640~
0x1641
0x1642~
0x1643
0x1644~
0x1645
0x1648~
0x1649
0x164A~0x
164B
0x164C~0x
164D
Short Term Power
voice detector
Long Term Power
Voice Detector
Voice Detector Power
Deviation
Short Term Power
Double Talk
Long Term Power
Double Talk
Double Talk Power
Deviation
Indicate Short Term Power calculated by the voice
detector (VD).
Indicate Long Term Power calculated by the voice
detector (VD).
Indicate Power Deviation estimated by the voice
detector (VD).
Indicate Short Term Power calculated by double-talk
detector (DT).
Indicate Long Term Power calculated by double-talk
detector (DT).
Indicate Power Deviation estimated by the double-talk
detector (DT).
R
R
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x00
R
R
R
R
0x1680
0x1681
0x1682
0x1683
0x1684
0x1685
AGC Control
R/W
R/W
R/W
R/W
R
Enable / Disable AGC and Set max gain control
Enable/Disable AGC initial gain setting
Set decreasing and increasing gain time for AGC
Set release time for AGC peak voice level
Indicate AGC gain status
AGC Initial Gain
Control
0x00
AGC Gain Time
0x00
AGC Peak Release
Time
0x00
AGC Gain Monitor
0x00
AGC Gain Region
Monitor
Indicate AGC gain status at increasing, target or
decreasing region.
R
0x00
0x1687~
0x1689
0x168A~0x
168B
0x168C~0x
168D
0x168E~0x
168F
AGC Short Term
Power
R
0x0000
0x0000
0x0000
0x0000
Indicate AGC Short Term Power estimation
Set AGC target region threshold
AGC Target Threshold
R/W
R/W
R/W
AGC Noise Low
Threshold
AGC Noise High
Threshold
Set AGC Noise low threshold level
Set AGC Noise high threshold level
7.11
USB Controller Registers
Value At
Reset
Address
Name
Mode
R/W
R/W
R/W
Function
0x1800
USB Enable
0x00
0x00
0x00
Enable/Disable USB 1.1 function control
0x1801~
0x1803
USB Interrupt Register
A
Set USB endpoints interrupt enable, status and clear.
Set USB endpoints interrupt enable, status and clear.
0x1804 ~
0x1806
USB Interrupt Register
B
18
Rev1.2
W681308
Value At
Function
Reset
Address
Name
Mode
R/W
R/W
0x1807 ~
0x1809
USB Interrupt Register
C
0x00
0x00
Set USB Audio Class interrupt enable, status and clear.
Set USB Control in/out Endpoint control
Endpoint 0 – Control
In/Out
0x1810
Control in Endpoint Data. Internal FIFO has 1 byte for
Control In transmission. If the 3rd Token byte is not equal
to 0x01 or 0x03 (HID set report application), this byte will
be transmitted instead of Control-IN FIFO and Interrupt-
IN FIFO content.
0x1811
Control In Data
R/W
0x00
0x1828 ~
0x182F
Control Out Data
R
R/W
R
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Control Out Endpoint receiving data.
Set ISO In/Out Endpoint control register.
Indicate ISO Sampling Frequency
Indicate Current Record Volume
Indicate Current Play Volume
Endpoint 1 and 2 –
ISO In/Out
0x1830
0x1831
Sampling Frequency
Record Volume
Play Volume
0x1832-
0x1833
R
0x1834-
0x1835
R
HID Control Out
Information
0x1836
0x1837
0x1838
0x1839
R
Indicate First Packet and Valid Length
Indicate Audio Path Max Volume Gain
Set HID Token 3rd byte
Max Volume
R
HID Token Information
HID Descriptor Length
ISO SYNC Speed
R/W
R/W
R/W
R/W
W
This register value must be equal to the USB descriptor
with respect to the HID return length
0x1840 ~
0x1847
Set ISO SYNC speed tuning parameter register.
Set Bulk In Endpoint control register
Endpoint 3 – Bulk In
Control Register
0x1848
0x1849
0x184A
0x184B
0x1850
Bulk In Data
Set Bulk In transmission data register except final data.
Set Bulk In transmission final data register.
Indicate Bulk In transmission data FIFO empty flag.
Set Bulk Out Endpoint control register
Bulk In Final Data
W
Bulk In FIFO Empty
Flag
R
Endpoint 4 – Bulk Out
Control Register
R/W
19
Rev1.2
W681308
Value At
Function
Reset
Address
0x1851
0x1852
0x1858
0x1859
0x1880
0x1881
0x1882
Name
Mode
R
Bulk Out FIFO Length
Bulk Out Data
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Indicate Bulk Out Endpoint receiving data FIFO length.
Bulk Out Endpoint receiving data FIFO.
Set Interrupt In Endpoint control register
Interrupt In Endpoint transmission data length
Enable ISO IN/OUT FIFO access by MCU
ISO OUT FIFO depth indication
R
Endpoint 5 – Interrupt
In Control Register
R/W
R/W
R/W
R
USB Interrupt Data
Length
USB ISO MCU Enable
USB ISO IN FIFO
Depth
USB ISO OUT FIFO
Depth
R
ISO IN FIFO depth indication
0x1883~
0x1884
USB ISO IN DATA
R/W
R
ISO IN data sample will be written by MCU
ISO IN data sample will be read by MCU
USB Descriptor
0x1885~
0x1886
USB ISO OUT DATA
0x2000-
0x21FF
USB Descriptor RAM
data filed
R/W
R/W
R/W
R/W
0x2200-
0x223F
HID Control-IN data
field
HID Control-IN data field
0x2240-
0x227F
HID Interrupt-IN data
field
HID Interrupt-IN data field
0x2300-
0x233F
HID Control-OUT data
field
HID Control-OUT data field
20
Rev1.2
W681308
8.
8.1
Microcontroller
Features
8-bit Turbo 8051 Microcontroller with 12/24/48 MHz speed
256 bytes of on chip internal data RAM and 1K bytes external data RAM
Instruction set compatible with Nuvoton Turbo 8051
Three 8-bit I/O ports
Three 16-bit timers
One Full-duplex serial port
On-Chip debugger via JTAG (Joint Test Access Group) port
7 interrupt sources with two level priorities
Programmable Watchdog Timer
Two 16-bit data pointers
On Chip 8 KB OTP (One time programmable) memory
8.2
Memory Organization
8.2.1
Program Memory
On-chip 8k OTP Memory:
All instructions are fetched for execution from this memory area. The MOVC instruction can also access this memory region.
8.2.2
Data Memory
The MCU can access 1K bytes of external Data Memory. This memory region is accessed by the MOVX instruction.
Additionally it has 256 bytes on chip RAM which can be accessed either by direct addressing or by indirect addressing.
Some Special Function Registers (SFRs) can only be accessed by direct addressing.
F F
1 F F F
Indirect RAM
Addressing
SFRs Direct
Addressing only
8K Byte
OPT Internal
ROM
8 0
7 F
Direct&Indirect
Addressing
33 F F
3 0 0 0
1K Byte
RAM
0 0
0 0 0 0
21
Rev1.2
W681308
8.2.3
Special Function Registers (SFR)
Address
Byte 0
EIP
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
B
EIE
ACC
WDCON
PSW
T2CON
T2MOD
SADEN
RCAP2L
RCAP2H
TL2
TH2
PMR
STATUS
TA
IP
P3
IE
SADDR
XRAMAH
SBUF
P2
SCON
P1
TCON
P0
TMOD
SP
TL0
TL1
TH0
TH1
CKCON
DPS
DPL
DPH
DPL1
DPH1
PCON
Table 2 W681308 MCU SFR location
8.3
Power Management
The W681308 has IDLE mode operation features that manage and save power consumption of the device.
Enable IDLE mode
The user can set the device into idle mode by writing 1 to the PCON bit of SFR. The instruction that sets the idle bit is the last
instruction that will be executed before the device goes into Idle Mode. In the Idle mode, the clock to the MCU is halted but
not to the Interrupt, Timer, Watchdog timer, and Serial ports blocks. This forces the MCU state to be frozen; the Program
counter, the Stack Pointer, the Program Status Word, the Accumulator and the other registers hold their contents. The ALE
and PSEN pins are held high during the idle state. The port pins hold the logical states they had at the time Idle was
activated.
The Idle mode can be terminated in two ways:
Activation of any enabled interrupt
Since the interrupt controller is still active, the activation of any enabled interrupt can wake up the processor. This will
automatically clear the Idle bit, terminate the Idle mode, and the Interrupt Service Routine (ISR) will be executed. After the
ISR, execution of the program will continue from the instruction which put the device into idle mode.
22
Rev1.2
W681308
Activation of reset
The Idle mode can also be exited by activating the reset. The device can be put into reset either by applying a high on the
external RST pin, a Power on reset condition or a Watchdog timer reset. The external reset pin has to be held high for at
least two machine cycles i.e. 8 clock periods to be recognized as a valid reset. In the reset condition the program counter is
reset to 0000h and all the SFRs are set to the reset condition. Since the clock is already running there is no delay and
execution starts immediately. In Idle mode, the Watchdog timer continues to run, and if enabled, a time-out will cause a
watchdog timer interrupt which will wake up the device. The software must reset the Watchdog timer in order to preempt the
reset which will occur after 512 clock periods of the time-out. When the W681308 is exiting from an idle mode with a reset,
the instruction following the one which put the device into idle mode is not executed. So there is no danger of unexpected
writes.
8.4
There are two ways to put device into reset state: external reset and watchdog reset.
8.4.1 External Reset
Reset Conditions
The device continuously samples the RST pin at state C4 of every machine cycle. Therefore the RST pin must be held for at
least 2 machine cycles to ensure detection of a valid RST high. The reset circuitry then synchronously applies the internal
reset signal. Thus the reset is synchronous operation and requires the clock to be running to cause an external reset. Once
the device is in reset condition, it will remain so long as RST is 1. Even after RST is deactivated, the device will continue to
be in reset state for up to two machine cycles, and then begin program execution from 0000h.
8.4.2
Watchdog Reset
The Watchdog timer is a free-running timer with programmable time-out intervals. The user can clear the watchdog timer at
any time, causing it to restart the count. When the time-out interval is reached an interrupt flag is set. If the Watchdog reset is
enabled and the watchdog timer is not cleared, then 512 clocks from the flag being set, the watchdog timer will generate a
reset. This places the device into the reset condition. The reset condition is maintained by hardware for two machine cycles.
Once the reset is removed the device will begin execution from 0000h.
8.5
Interrupts
The W681308 MCU has three priority levels interrupt structure with 7 interrupt sources. Each of the interrupt sources has an
individual priority bit, flag, interrupt vector and enable bit. Additionally, all the interrupts can be globally enabled or disabled.
Source
Flag
IE0
Priority
Vector address
0003h
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port
1 (highest)
TF0
2
000Bh
IE1
3
0013h
TF1
4
001Bh
RI + TI
TF2 + EXF2
WDIF
5
6
0023h
Timer 2 Overflow
Watchdog Timer
002Bh
7 (lowest)
0063h
Table 3 Interrupt Priority Structure
23
Rev1.2
W681308
8.6
Programming Timers and Counters
The MCU of W681308 has three 16-bit programmable timers/counters and one programmable Watchdog timer. The
Watchdog timer is operationally quite different from the other three timers.
8.6.1
Timers/Counters 0 and 1
Timer 0 (TM0) and Timer 1 (TM1) are 16-bit Timer/Counters and are nearly identical. Each of these Timers/Counters has two
8 bit registers which form the 16 bit counting register. For Timer/Counter 0 they are TH0, the upper 8 bits register, and TL0,
the lower 8 bit register. Similarly Timer/Counter 1 has two 8 bit registers, TH1 and TL1. The two timers can be configured to
operate either as timers to count machine cycles or as counters counting external inputs.
In Timer mode, the timer counts clock cycles. The timer clock can be programmed to be thought of as 1/12 of the system
clock or 1/4 of the system clock.
In Counter mode, the register is incremented on the falling edge of the corresponding external input pins, T0 for Timer 0 and
T1 for Timer 1. The T0 and T1 inputs are sampled in every machine cycle at C4. If the sampled value is high in one machine
cycle and low in the next, then a valid high to low transition on the pin is recognized and the count register is incremented.
Since it takes two machine cycles to recognize a negative transition on the pin, the minimum period at which counting will
take place is double of the machine cycle.
In either the Timer or Counter mode, the count register will be updated at C3. Therefore, in the Timer mode, the recognized
negative transition on pin T0 and T1 can cause the count register value to be updated only in the machine cycle following the
one in which the negative edge was detected.
The Timer or Counter function is selected by the C/T bit in the TMOD Special Function Register. Each Timer/Counter has
one selection bit for its own. Bit 2 of TMOD selects the function for Timer/Counter 0 and bit 6 of TMOD selects the function
for Timer/Counter 1.
89H
TMOD
88H
Bit 7
GATE
Bit 7
Bit 6
C/T
Bit 5
M1
Bit 4
M0
Bit 3
GATE
Bit 3
IE1
Bit 2
C/T
Bit 2
IT1
Bit 1
M1
Bit 0
M0
Bit 6
TR1
Bit 5
TF0
Bit 4
TR0
Bit 1
IE0
Bit 0
IT0
TCON
TF1
Table 4 Timer Mode/Control TMOD/TCON SFR
24
Rev1.2
W681308
8.6.2
Timer/Counter 2
Timer/Counter 2 is a 16 bit up/down counter which is configured by the T2MOD register and controlled by the T2CON
register. Timer/Counter 2 is equipped with a capture/reload capability. As with the Timer 0 and Timer 1 counters, they
provide wide selection and control of the clock and selection of the operating modes. The clock source for Timer/ Counter 2
can be selected for the crystal oscillator, which is divided by 12 or 4 ( C/T2 = 0). The clock is then enabled when TR2 is a 1,
and disabled when TR2 is a 0.
C9H
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
T2CR
EXEN2
Bit 2
-
Bit 1
-
Bit 0
T2MOD
T2CON
DCEN
CP/RL2
TF2
EXF2
RCLK
TCLK
TR2
C/T2
Table 5 Timer 2 Mode/Control TMOD/TCON SFR
8.6.3
Watchdog Timer
The Watchdog timer is a free-running timer that can be programmed by the user to serve as a system supervisor, a time-
base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable
and determines the time-out interval. When the time-out occurs the flag WDIF is set, which can cause an interrupt if enabled,
and a system reset can also be caused if it is enabled. The interrupt will occur if the individual interrupt enable and the global
enable are set. The interrupt and reset functions are independent of each other and may be used separately or together
depending on the software employed.
Fosc
12/24/
48MHz
WD1,WD
0
22
0
Interru
pt
WDIF
EWD(EIE.4
00
01
10
11
)
23
26
24
WTRF
Time-out
25
512
clock
delay
Res
et
27
Enable Watchdog timer
Reset
Watchdog
PWT(WDCON.
reset
EWT(WDCON.1)
When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the WDIF flag each time the
timer completes the selected time interval. The WDIF flag is polled to detect a time-out and the RWT allows software to
restart the timer. The Watchdog timer can also be used as a very long timer. The interrupt feature is enabled in this case.
Every time the time-out occurs an interrupt will occur if the global interrupt enable EA is set.
25
Rev1.2
W681308
The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of
some power glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is left
unchecked the entire system may crash. Using the watchdog timer interrupt during software development will allow the user
to select ideal watchdog reset locations. The code is first written without the watchdog interrupt or reset. Then the watchdog
interrupt is enabled to identify code locations where interrupt occurs. The user can now insert instructions to reset the
watchdog timer which will allow the code to run without any watchdog timer interrupts. Now the watchdog timer reset is
enabled and the watchdog interrupt may be disabled. If any errant code is executed now, then the reset watchdog timer
instructions will not be executed at the required instants and watchdog reset will occur.
Watchdog
Interval
Number of
Clocks
WD1
0
WD0
0
Time@12MHz
699.05 ms
Time@24MHz
349.53 ms
Time@48MHz
174.76 ms
223
225
226
228
8388608
33554462
67108864
268435456
0
1
1
1
0
1
2796.20 ms
5592.41 ms
22369.62 ms
1398.10 ms
2796.20 ms
11184.81 ms
699.05 ms
1398.10 ms
5592.41 ms
Table 6 Time-Out Values For Watchdog Timer
The Watchdog timer will be disabled by a power-on/fail reset. The Watchdog timer reset does not disable the watchdog timer,
but will restart it.
NOTE: In general, software should restart the timer to put it into a known state.
D8H
Bit 7
-
Bit 6
POR
Bit 5
-
Bit 4
-
Bit 3
Bit 2
Bit 1
Bit 0
WDCON
WDIF
WTRF
EWT
RWT
External
Reset
0
x
0
x
0
x
x
0
Table 7 Watchdog Control WDCON SFR
Control Bit
POR
Name
Function
Hardware will set this flag on a power up condition. This flag can be read or written
by software. A write by software is the only way to clear this bit once it is set.
Power-on Reset Flag
This bit is set by hardware to indicate that the time-out period has elapsed and
invoke watch dog timer interrupt if enabled(EWDI=1). This bit must be cleared by
software.
Watchdog Timer
Interrupt Flag
WDIF
Hardware will set this bit when the watchdog timer causes a reset. Software can
read it but must clear it manually. A power-fail reset will also clear the bit. This bit
helps software in determining the cause of a reset. If EWT = 0, the watchdog timer
will have no affect on this bit.
Watchdog Timer
Reset Flag
WTRF
26
Rev1.2
W681308
Control Bit
EWT
Name
Function
Enable Watchdog
timer Reset
Setting this bit will enable the Watchdog timer Reset function.
This bit helps in putting the watchdog timer into a know state. It also helps in
resetting the watchdog timer before a time-out occurs. Failing to set the EWT before
time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a
watchdog timer reset will be generated if EWT is set. This bit is self-clearing.
Reset Watchdog
Timer
RWT
Table 8 Watchdog Control Bits
WTRF is set to a 1 on a Watchdog timer reset, set to 0 on power on/down resets. WTRF is not altered by an external reset.
POR is set to 1 by a power-on reset. EWT is cleared to 0 on a Power-on reset and unaffected by other resets.
To prevent software from accidentally enabling or disabling the watch dog reset function, the bit of WDCON requires Time
Access (TA) procedure to write.
Example:
mov TA, #0AAH
mov TA, #055H
clr WDIF
WD1, WD0 are Time-out bits for Watchdog Timer located at CKCON.7 and CKCON.6. These bits determine the time-out
period of the watchdog timer. The reset time-out period is 512 clocks longer than the watchdog time-out.
WD1
WD0
Interrupt time-out
Reset time-out
223 + 512
0
0
1
1
0
1
0
1
223
225
226
228
225 + 512
226 + 512
228 + 512
Table 9 Watchdog Timer Timeout Control
27
Rev1.2
W681308
8.7
Serial Port (UART)
The MCU serial port is a full-duplex port, and the MCU provides additional features, such as Frame Error Detection and
Automatic Address Recognition. The serial port is capable of synchronous and asynchronous communication. In
synchronous mode, the MCU generates the clock and operates in half-duplex mode. In asynchronous mode, the serial port
can simultaneously transmit and receive data. The transmit register and the receive buffer are both addressed as SBUF, but
any write to SBUF writes to the transmit register while any read from SBUF reads from the receive buffer. The serial port can
operate in four modes: MOD 0, MOD 1, MOD 2 and MOD 3.
98H
Bit 7
Bit 6
SM1
Bit 5
SM2
Bit 4
REN
Bit 3
TB8
Bit 2
RB8
Bit 1
TI
Bit 0
RI
SCON
SM0/FE
Table 10 Serial Control SCON SFR
8.8
The W681308 internal OTP ROM is designed to store all application firmware.
8kB One-Time Programmable Logic Device
OTP ROM
The OTP programming is done by the injection of hot electrons which are generated by avalanche impact ionization in the bit
cell. User can enter JTAG mode to program 8k OTP ROM through JTAG interface pins and signal of PCMT pin will go high
simultaneously. The signal of pin PCMT can be used to control external hardware device to apply 6.75V or 3.3V to
programming voltage pin VPP. The cells are initialized by ultraviolet light through internal photoemission from the floating
gate.
Enable OTP Read Protection
You can write zero to bit 7 of OTP address 0x1fff to turn on the read protection feature.
28
Rev1.2
W681308
9.
9.1
Clock Control and Reset
Clock Control
9.1.1
Overview
Each register in the 12/24/48 MHz USB Audio Controller is reset synchronously. The Reset and Clock Control function
ensures that the system reset signal is correctly generated. The system reset signal is also used to ensure that bi-directional
signals are all set to input during initialization.
9.1.2
Clock Generation
The crystal oscillator circuit and the external attachment of a 12 MHz quartz crystal or ceramic resonator is shown below.
The Rf is used to DC bias the internal amplifier to operate in the linear region. The R1, C1, and C2 are chosen so as not to
overdrive the crystal and to suppress oscillation at higher harmonics. Rf = 1MΩ, R1=270Ω, C1 and C2 are to be 33pf each.
XTAL_IN
XTAL_OUT
R1
Rf
External
Crystal
C2
C1
The PLL block diagram is shown below. The PLL uses the output of the crystal oscillator as its reference clock and generate
a 48 MHz clock.
29
Rev1.2
W681308
9.1.3
Control Register
MCU Rate Select
Address
0x1440
Access Mode
R/W
Value At Reset
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
MCU Rate Select [7:6]
Reserved
Reserved
Reserved
Reserved
Reserved
MCU Rate Select [7:6]
MCU Clock Rate select (default = 00 )
00 = 12 MHz , Use for CODEC/AEC/USB Controller
01 = 24 MHz
10 = 48 MHz , Use for MCU/USB PHY/Peripherals
11 = Reserved
30
Rev1.2
W681308
10.
10.1
Interrupt Control
Overview
The W681308 generates internal events, these interrupt events are triggered by the interrupt control logic. The MCU
supports two priority levels of interrupts with 6 interrupt sources.
10.2
Functionality
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered,
The Interface and Support logic generate the following interrupts:
NFS interrupt
Keypad-Wakeup Interrupt
GPIO interrupt
SPI interrupt
W2S interrupt
USB interrupt
Three registers control the generation of interrupts in the W681308, the interrupt source register, the interrupt enable register
and the interrupt priority register. Each interrupt has a corresponding bit in these three registers.
The interrupt source register is set when an interrupt event occurs and is cleared by MCU.
When the MCU writes to interrupt source, any bit that is set to 1 cause the corresponding bit of interrupt source to be cleared,
bits set to 0 are not affected (write “one” to clear).
An Interrupt is generated when (interrupt source) & (interrupt enable) =1 for any of the interrupt sources. For each bit; if
interrupt priority = 0, the interrupt is issued to INT0, if interrupt priority = 1, the interrupt is issued to INT1.
Interrupt
Source
&
INT0
&
Interrupt
Enable
INT1
&
Interrupt
Priority
Figure 3 Interrupt Structure
31
Rev1.2
W681308
10.3
Interrupt Control Registers
Address
0x1441 ~ 0x1443
Access Mode
R/W
Value At Reset
0x00
Address
0x1441
Bit 7
Bit 6
W2S
Bit 5
SPI Interrupt
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Keypad-
USB
Interrupt
GPIO
Interrupt
Wakeup NFS Interrupt Reserved
Interrupt
Reserved
Interrupt
NOTE: The NFS interrupt occurs for every 8 CODEC frames.
Interrupt Source Register
(0x1441)
Interrupt Enable Register
(0x1442)
Interrupt Priority Register
(0x1443)
Read: 1 = Interrupt 0 = No Interrupt
Write: 1 = Clear
1 = Enable
0 = Disable
0 = INT0
1 = INT1
32
Rev1.2
W681308
11.
Interface Logic
The W681308 Interface logic consists of:
Keypad Scanner Interface
Input/Output GPIO Ports
LCD/LCM interface
UART interface
JTAG Interface
PCM Interface
SPI for Serial Data Flash
W2S Interface
Keypad scanner, GPIO, LCD/LCM and UART interfaces are covered in this section.
11.1
Software Keypad Scanner
The keypads consist of a number of buttons, connected in a row/column arrangement as shown in
Figure 4 The default pin KX[4:0] is pull-L and pin KY[4:0] is pull-H, User can follow below steps to scan the keypad by
software:
1. Program KX[4:0] pin to output direction and output data 0. Program KY[4:0] pins to input direction.
2. While key is pressed, MCU will be informed by GPIO interrupt then to check KX[4:0] and KY[4:0] status.
3. KX[4:0] keep output data 0, then to read KY[4:0] status by register 0x1451[4:0], By reading
can know which bit equal 0, allowing it to determine which row is pressed.
KY[4:0] status, MCU
4. Change pin KY[4:0] from input direction to output direction and output data 1. Change pin KX[4:0] from output
direction to input direction then to read KX[4:0] status by register 0x1450[4:0]. By reading KX[4:0] status, MCU can
know which bit equal 1, allowing it to determine which column is pressed.
5. MCU knows which row and column are pressed, so it can determine which key is pressed.
S1
S2
S3
S4
S5
KY[0]
KY[1]
KY[2]
KY[3]
KY[4]
S6
S7
S8
S9
S10
S15
S20
S25
S11
S16
S21
S12
S17
S22
S13
S18
S23
S14
S19
S24
KX[0]
KX[1]
KX[2]
KX[3]
KX[4]
Figure 4 Keypad Scanning Application Circuit
33
Rev1.2
W681308
11.2
GPIO s
W681308 has 25 GPIO pins that are mainly used for keypad scanner, LCM controller, SPI, W2S, PCM interface, UART port,
JTAG interface and GPIO s.
NOTE: The pin function for LED, CS, SCLK, SDI, SDO and CSL will act as different functions according to the setting of
LCD_ENB (0x145E), SPI_ENB (0x14A0), RDY_ENB(0x14AB) and W2S_ENB(0x14B0).
Address
0x145E[3]
0x14A0[7]
0x14AB[5]
0x14B0[7]
Name
Values
LCD_ENB
SPI_ENB
RDY_ENB
W2S_ENB
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
Functions
Pin Number
Pin Name
0x145E[2:0]
for LCD driver
Control
SPI for LCD
driver
SPI for
data flash
GPIO
ISD15000
W2S
11
13
14
15
16
17
LED
CS
GPIO 3
GPIO 11
GPIO 10
GPIO 9
GPIO 8
GPIO 12
GPIO 03
GPIO 11
GPIO 3
SPI_CS
SPI_CLK
GPIO 9
GPIO 3
SPI_CS
SPI_RDY
SPI_CS
GPIO 3
GPIO 11
W2S_SCL
GPIO 9
LCD_CKN
(0x145E[B1])
SCLK
SDI
SPI_CLK
SPI_SDI
SPI_SDO
GPIO 12
SPI_CLK
SPI_SDI
SPI_SDO
GPIO 12
GPIO 09
LCD_TX
(0x145E[B0])
LCD_CSN
SDO
CSL
SPI_DO
Pull High
W2S_SDA
GPIO 12
(0x145E[B2])
34
Rev1.2
W681308
11.3
LCD Control
Address
0x145E
Access Mode
R/W
Value At Reset
0x00
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
LCD_ENB
LCD_CSN
LCD_CKN
LCD_TX
LCD_TX
LCD Write Out Data
LCD Write Out Clock
LCD Write Out Chip Select Enable (active low)
LCD I/O Enable Control : 1 = Enable, 0 = Disable
Set this bit to enable LCD control interface :
Pin 17 CSL = LCD_CSN
LCD_CKN
LCD_CSN
LCD_ENB
Pin 14 SCLK = LCD_CKN
Pin 16 SDO = LCD_TX
11.4
UART I/O Control
Address
Access Mode
R/W
Value At Reset
0x00
0x145F
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
UART IO ENB
UART IO ENB
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UART I/O Enable Control, 1 = Enable, 0 = Disable
35
Rev1.2
W681308
12.
12.1
PCM Interface , Gain Stage and Mixer
PCM Interface
The PCM module is a 16-bit parallel/serial data transfer interface. It transfers the 16 bits data from Gain-Stage/Mixer to single
bit Output, and transfers the one bit signal data of Input pin to 16 bits data buffer to the Gain-Stage / Mixer. In normal
operation, the FS and BCLK are generated from the analog PLL module.
PCM Interface specification:
Master Mode Only
Support TX / RX path mute
8 PCM Bit Clock frequency : 128K, 256K, 512K, 768K, 1M, 1.536M, 2M, 4M Hz.
3 frequency selection of the PCM Frame Sync (FS) : 8K, 16K and 48K Hz.
16 bit length selection of the PCM Frame Sync (FS) : 1~ 16 bits.
4 selection of PCM FS/DATA location + 1 half bit clock delay.
PCM_FS & PCM_BCLK inverse mode for I2S interface.
12.2
Gain stage
There are 6 programmable gain stages for transmit and receive path. These gain stages are implemented to provide a range
of +24 dB to –31.5 dB with 0.5 dB per step. The Figure 5 is shown the location of these digital gain stages. There are 2 side
tone paths to select from: One before AEC block, one after AEC block. Side tone gain stage is from -0.5dB to -31.5dB with
0.5dB step.
Figure 5 PCM Interface, Gain Stage and Mixer Location
36
Rev1.2
W681308
12.3
Mixer
The mixer provides flexible connections among CODEC block, PCM interface and USB block. We will describe each
connection case of mixer modes and how to configure them below.
12.4
Connection Case Example
Figure 6 Mixer Connection Case Examples
Case 0: Link CODEC and USB
Case 1: Link CODEC and PCM
37
Rev1.2
W681308
Case 2: Link PCM and USB
Case 3: Link All
12.5
38
Rev1.2
W681308
Mixer Case Examples with Register Setting
Figure 7 Mixer Examples with Registers Setting
Case 0: Default
Register Setting:
0x1460 = 0x80 (Enable Gain Stage, Link CODEC_USB)
0x1470 = 0x00 (Disable PCM)
Case 1: Record Conversation
Register Setting:
0x1460 = 0x83 (Enable Gain Stage, Link All)
0x1470 = 0x80 (Enable PCM)
0x1474 = 0x02 (Mute PCM_RX)
39
Rev1.2
W681308
Case 2: Record Greeting
Register Setting:
0x1460 = 0x80 (Enable Gain Stage, Link CODEC_USB)
0x1470 = 0x80 (Enable PCM)
0x1474 = 0x02 (Mute PCM_RX)
Case 3: Record Message
Register Setting:
0x1460 = 0xF0 (Enable Gain Stage, Link CODEC_USB, Record_USB)
0x1470 = 0x80 (Enable PCM)
0x1474 = 0x02 (Mute PCM_RX)
40
Rev1.2
W681308
Case 4: Play conversation 1
Register Setting:
0x1460 = 0x83 (Enable Gain Stage, Link All)
0x1470 = 0x80 (Enable PCM)
0x1474 = 0x04 (Mute PCM_TX)
Case 5: Play Conversation 2
Register Setting:
0x1460 = 0x83 (Enable Gain Stage, Link All)
0x1470 = 0x80 (Enable PCM)
0x1474 = 0x04 (Mute PCM_TX)
0x1464 = 0x40 (Mute CODEC A/D IN)
0x1467 = 0x40 (Mute USB ISO OUT)
41
Rev1.2
W681308
Case 6: Pro-X FXS
Register Setting:
0x1460 = 0x81 (Enable Gain Stage, Link PCM_USB)
0x1470 = 0x80 (Enable PCM)
0x1465 = 0x40 (Mute CODEC D/A OUT)
12.6
I2S Register Setting Example
The following example will generate I2S interface format from the W681308 PCM interface.
I2S for 48KHz Sampling Rate(SR) with 16bits LPCM :
0x1470 = 85
0x1470 [2:0]
101 = BCLK Rate Select. SR x 32 bits = 48K x 32 = 1.536MHz ( L,
R channels are 16 bits format)
00 = FST Location, Frame Sync is occurred before the MSB of the
PCM data.
0x1470 [4:3]
0x1470 [7]
0x1472
1 = Enable PCM Interface
F0 = For long frame
0x1474
40 = PCM bit clock inverse enable
42
Rev1.2
W681308
13.
13.1
Audio Codec Interface
Overview
The audio CODEC interface allows the USB Audio Controller Device to be connected to one or more of the following:
16 bit internal linear PCM CODEC and Echo Cancellation block.
8/16/48 KHz CODEC sampling rate
An I2S interface to and from the on chip linear CODEC.
A PCM interface to connect to a external Nuvoton ProX SLIC/CODEC
The audio data is flowing between USB interface and CODEC through 2 segmented FIFOs that allow MCU processing of
audio data.
13.2
Audio CODEC Signal Path
Figure 8 W681308 CODEC Signal Path Control
Transmit Path Operation
The microphone is biased through pins MCP by an internal programmable voltage reference and programmable resistor. The
microphone ac signal is gained up by the input amplifier and filtered to prevent aliasing at the input of the sigma delta ADC.
The sigma delta ADC converts the signal in a 2 bit digital representation, which is decimated and low pass filtered to the
base band sampling rate of 8kHz to 48kHz. A high pass filter can be enabled in the transmit path.
43
Rev1.2
W681308
The signal from the digital receive input is filtered through the acoustic echo cancellation filter and subtracted from the high
pass filter output. The acoustic echo cancellation is only active in speaker phone operation with 8 kHz sampling. The result is
then passed to the AGC with programmable time, release time and enable signal. The output of the AGC can be passed
either to the PCM interface, the USB/MCU or both (recording a conversation).
Receive Path Operation
The PCM input can be obtained through a multiplexer from the PCM interface or the USB FIFO/MCU. The digital signal can
then be gained or attenuated through a programmable digital gain stage. Then, the side tone from the transmit side is added
through a programmable side tone gain stage. The side tone is disabled when the speakerphone is active.
The digital signal is then passed through a high pass filter with programmable enable. The output of the high pass filter goes
through the interpolation smoothing filter, which produces a 4 bit binary to 15 bit thermometer digital representation for the
sigma delta DAC. The output of the DAC goes through an analog smoothing filter. The output of the smoothing filter can be
hooked up to the speaker phone speaker driver, the earphone speaker driver or both.
A programmable attenuation switch is used to switch between the earphone driver and the speaker phone driver. At power
up of the analog section, the slow ramp on pin VREF1 is used to control the ramp up of the speaker and earphone driver in
order to avoid ‘POP’ sounds. During operation, the user should lower the volume of the speaker using the software volume
control settings, before switching the speaker and earphone driver in order to reduce the ‘POP’ sounds.;
Alternatively, a buzzer can be used on the speakerphone driver outputs, using a 200Hz- 32 kHz PWM signal. However, the
speakerphone can not be used in that case.
Digital CODEC
The digital CODEC filter chain is so designed that it can handle 48K, 16K and 8K rate through its rate change filters.
13.3
Microphone Interface and Auxiliary Interface
W681308 integrates a fully programmable microphone interface. No external components other than the microphone are
required to operate the circuit. The microphone interface can operate in three modes:
Voltage gain mode
Current gain mode
Auxiliary input mode
For the Current gain mode an internal or external resistor can be selected to determine the gain. The Auxiliary input mode
should be used with external resistors. However, an internal gain resistor can be selected. The interface modes above can
be selected with register MIC_MODE [2:0] at address 0x1489.
Voltage Gain Mode
The basic operation is shown below in
Figure 9. The microphone is connected to the pins MCP and RGND. It is important that the negative terminal of the
microphone is routed separately to the RGND pin for ‘pseudo differential’ operation, reducing the background noise amplified
by the microphone amplifier. This can be enforced in the PCB layout by placing a 0 Ohm resistor or a ferrite bead. The pin
MCO is connected to the output of the microphone amplifier and can be used for monitoring the AC level. The voltage gain is
set by register MIC_GAIN[7:4] at address 0x1489. This register provides a gain range from 14dB to 38dB. The gain is set by
a ratio of internal resistors, providing accurate gain control. The pin MCP also supplies the bias reference for the microphone.
The bias consists of a programmable resistor and a programmable voltage reference. The programmable resistor is set by
register MIC_RES[7:4] at address 0x1488 and can be set to open and 670 Ohm to 10kOhm. The programmable voltage
reference is set by register MIC_BIAS[2:0] at address 0x1488 and can be set from 1.22Volt to 2.74Volt.
44
Rev1.2
W681308
MIC_BIAS[2:0]
0x1488
W681308
Voltage Gain Mode
0x1489
MIC_MODE=‘000’
MIC_RES[7:4]
0x1488
MCP
+
-
To ADC
Electret
Microphone
MIC_GAIN[7:4]
0x1489
RINT1
RINT2
MIC_GAIN[7:4]
0x1489
MCO
250 Ohm
V
V
ADC
MCP
R
INT 1
RGND
=1+
Rm
0 Ohm
Or ferrite
RINT 2
'000'
Figure 9 Microphone Voltage Gain Mode
Current Gain Mode
For higher gain configurations, the current gain mode can be used as in
Figure 10 below.
MIC_BIAS[2:0]
0x1488
W681308
Current Gain Mode
0x1489
MIC_MODE=‘010’or ‘011’
MIC_RES[7:4]
0x1488
MCP
IS
+
-
To ADC
Electret
Microphone
IS
MIC_GAIN[7:4]
0x1489
Rinternal
0x1489
RINT
MCO
250 Ohm
V
I
ADC
= −(REXT+ 250)
= −RINT
S
'011'
'010'
V
I
ADC
RGND
S
Rm
0 Ohm
Or ferrite
R
EXT > 20kΩ
Figure 10 Microphone Current Gain Mode
45
Rev1.2
W681308
The current gain mode uses the same programmable microphone bias voltage and resistor as the voltage gain mode. The
gain is set by either the internal gain resistor or an external resistor, depending on the MIC_MODE setting. Since the current
gain mode is using a single resistor, the gain accuracy is limited. However, large gain can be achieved. Note that a 250Ohm
ESD protection resistor is connected to the MCO pin. This resistor should be considered when calculating the gain.
Auxiliary Input Mode
For non-microphone applications one or more Auxiliary inputs can be connected to the MCP pin as shown in
Figure 11 below. The MIC_RES register should be set to open in order to disconnect the microphone bias. For the gain
setting it is advised to use external gain resistors only for optimal matching and accuracy. The 250Ohm ESD protection
resistor should be considered again when calculating the gain. Note that for this mode the RGND pin is tied to the external
supply ground. A clean ground reference should be used for this.
MIC_BIAS[2:0]
0x1488
W681308
Auxiliary Input Mode
0x1489
MIC_MODE[2:0]=‘101’
MIC_RES[7:4]
0x1488
=‘0100’
Cs1
Csn
Rs1
MCP
+
-
To ADC
+
Vs
-
MIC_GAIN[7:4]
0x1489
Rsn
+
Vsn
-
Rinternal
0x1489
MCO
V
ADC
R
EXT+ 250
250 Ohm
= −
V
S
R
S
'101'
R
EXT > 20kΩ
RGND
1
C
S
=
40⋅π⋅R
S
Figure 11 Microphone Auxiliary Input Mode
46
Rev1.2
W681308
14.
14.1
Serial Peripheral Interface
Overview
W681308 built in a serial peripheral interface (SPI) port which is a 4-pin (SCLK, CS, SDI, SDO) SPI Interface. This SPI
interface makes W681308 an easy to control 4-pin SPI device including SPI data flash, SPI LCM, Nuvoton Pro-X SLIC
CODEC etc. This device has various clock speed and data format by setting relative control registers. The SPI module can
be operated at clock rates of up to MCU clock rate.
Figure 12 SPI Block Diagram
14.2
Data and Signal Format of SPI
There are 5 control bits (CSN_ADD, CSN_MORE, CK_MORE, CP and CI) to decide the SPI control signal format. Register
0x14AB has detail description of the control bits.
The packet and page data format is separated to 2 fields: Command field and the Data field. Command field (0 ~ 5 bytes)
consists of control instruction/code and access address (TX only). Data field (0 ~ 256 bytes) consists of write and read data
of serial data flash (TX/RX). All Command and Data bytes are send MSB first. Command and Data field length can be
programmed in CMD_LEN (0x14A1[2:0]) and DATA_LEN (0x14A2[7:0]) register fields. It can be bypassed to write control bit
CMD_BYPASS or disable the DATA_ENB. The max command field length is 5 bytes. The max data field length is 256 bytes
in unidirectional mode, and 128 bytes in bidirectional mode. Thirteen examples are provided for reference.
14.3
FSM of SPI
There are 3 states in the SPI Finite State Machine (FSM) module. The initial state is IDLE when power on.
IDLE
After enable the SPI function (write 0x14A0[7] =1), the FSM start to wait for MCU control (write 0x14A1) to change to next
state. If the CMD BYPASS flag (0x14A1[5]) is true, the FSM will change to DATA state, then force control logic to shift in/out
the data bytes sequentially. If the CMD BYPASS flag ( 0x14A1[5]) is false, the FSM will change to the CMD state, then force
control logic to shift out the command bytes sequentially to external SPI device.
Command (CMD)
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Rev1.2
W681308
After finished shift out the command bytes, the FSM will change to DATA state if the Data_enb ( 0x14A1[4]) is true, or run
back to IDLE state if the Data_enb is false.
Data
When FSM goes into Data state, the control logic start to shift out write data to external SPI device if SPI_RD (0x14A1[3]) is
false, or shift in read data from external SPI device if SPI_RD (0x14A1[3]) is true. In bidirection mode, the control logic will
ignore SPI_RD (0x14A1[3]) and start to shift in/out the read/write data from/to external SPI device. After finishing shift out/in
the data bytes, the FSM will go back to IDLE state and wait for next transition.
IDLE
DATA
CMD
14.4
FIFO and RAM of SPI
The SPI module takes up to 5 bytes Register to write the control command and takes the 256x8 bytes RAM to do the
Read/Write access FIFO. In Bidirectional mode, the 256x8 bytes RAM will separate into two 128x8 bytes sections. One
(ADDR: 0x00~7F) for keep the transmit data, and the other one (ADDR: 0x80~0xFF) for store the receive data. Once the
Bidirectional mode is enabled, the SPI module will automatic put receive data from ADDR: 0x80 instead of the ADDR: 0x00
as in the unidirectional mode. It supports two memory access methods:
FIFO like method
MCU always read/write the same register (0x14AC) with hardware control the memory read/write address, and increase the
read/write pointer automatically after each read/write. The current write and read pointer can be read at register 0x14AE and
0x14AF.
Direct access method
MCU can read/write any byte of the memory after setting the read (0x14AF)/write (0x14AE) pointer first.
14.5
Interrupt Sources
The SPI module supports two types of interrupt sources:
TX/RX finish interrupt
When TX/RX byte counts (0x14AD) = DATA_LEN.
Middle flag interrupt
When TX/RX byte counts (0x14AD) = 16 * INTR_CNT (0x14A3[7:4]).
For any other options, refer to the description of the specific registers in W681308 Design Guide.
48
Rev1.2
W681308
15.
15.1
Nuvoton 2-Wire Serial Bus
Overview
Nuvoton 2-wire serial bus (W2S) is a simple bi-directional 2-wire bus for efficient inter-IC control. This design is for W2S
master use only, and governed by the MCU. The W2S is used to both read/write EEPROM and to control various device
included I2C interface. The W2S controller is equipped with 35 bytes FIFO performing formatting and de-formatting. The
MCU can simply fill up the FIFO contents which consists of target device ID, high/low address (depend on the device format);
for reading, just set read enable, for writing, keep writing data to FIFO then set write enable to launch transmission. The W2S
controller supports 3 types of page writing, 8, 16 and 32 bytes. The W2S controller is designed to support maximum of 32
bytes per page. The FIFO depth can support 3 header bytes (one device ID, two address) and 32 bytes data. It has various
bus speed configurations to support wide range of EEPROM bus speed.
16.
16.1
ICE Function By JTAG STD. IEEE 1149.1
Overview
The W681308 MCU on-chip debugger function follows the JTAG standard. It provides 8 sets of breakpoints. There is no
watchpoint. There are five JTAG-style scan chains within the 8051 and peripheral logic, which enable embedded ICE logic.
The 5 JTAG interface pins TCK (JTAG test clock input), TMS (JTAG test mode select), TDI (JTAG test data input), TDO
(JTAG test data output) and nTRST (JTAG TAG controller reset) are needed to enable the operation. The JTAG interface
pins are multiplexed with other function pins.
16.2
Scan Chains and JTAG Interface
There are five JTAG-style scan chains within the TB51 core and peripheral logic interface. These enable debugging
operation and configuration of Embedded-ICE logic. An external pull low signal on nTRST will reset TAP controller or MCU
power-on reset will trigger TAP controller reset once.
16.3
Pin Description
Table 11 JTAG Pin Description
Pin Name
Type
Function
TCK
TMS
TDI
IN
IN
JTAG Test clock with internal pull-up.
JTAG Test-Mode Select with internal pull-up.
IN
JTAG Test Data Input with internal pull-up. TDI is latched on a rising edge of TCK.
JTAG Test Data Output. Data is shifted out on TDO at the rising edge of TCK. TDO
output is a tri-state driver with internal weakly pull-low resister.
TDO
nTRST
OUT
IN
JTAG TAP controller reset input with internal pull-up.
49
Rev1.2
W681308
16.4
Reset Behavior
TB51 will start to execute internal code after power on reset. If host JTAG ICE connects with TB51, the host ICE can send
command to control the TB51.
Reset type
Functional description
1. Reset MCU
Power On Reset
2. Reset JTAG. TAP controller will stay in Test-Logic Reset State.
3. Execution starts from address 0000 after reset.
1. Reset Chip.
Reset by RESET pin or WDT
2. Do not reset JTAG. TAP controller stays in the original state.
RESET (including set Reset
3. If the original TAP controller state is in run mode, chip reset
out and Reset in SC0)
4. If the original TAP controller state is in Halt mode. No any state changed
nTRST Low
1. No effect on MCU.
2. Reset JTAG. TAP controller will stay in Test-Logic Reset state.
17.
17.1
Ring Tone (PWM) Generator
Overview
The ring tone or PWM can generate dual frequency tones through on chip speaker driver. There are two tone signals can be
mixed to the speakerphone driver output. This subsection describes the Ring Tone Generator with the PWM (Pulse Width
Modulation) format.
Ring tone generator (PWM) specification:
Tone Channel Number = 2
Tone Volume Step = 32
Tone Frequency Range = 91Hz~23KHz
12M
Frequency =
Hz
N =1~ 256
16× N ×32
The tone frequency/volume control signal path is shown as Figure 13.
Figure 13 Ring Tone Generator Block
50
Rev1.2
W681308
18.
FULL/HALF DUPLEX ACOUSTIC ECHO CANCELLATION(AEC)
The AEC unit removes the echo signal caused by the speaker and room reflections.
18.1
Function Control Registers
Figure 14 illustrates the block diagram of the Full/Half Acoustics Echo Cancellation
Figure 14 Signal flow through Acoustic Echo Cancellation in the speech processor
51
Rev1.2
W681308
19.
USB Device Controller And Transceiver
Overview
19.1
The W681308 includes a full function USB 2.0 Full Speed controller. It supports USB 2.0 FS standard specification and
standard USB audio device class and HID device class in Microsoft Windows environment. The USB core embeds one
programmable 512x8 Bit RAM to store descriptor. In the setting, the USB core includes five interfaces and 6 endpoints to
handle above applications.
19.2
Functional Description
The USB function block diagram is shown below:
uC
ADDR_SEL
Control
Endpoint
#0
Descriptor RAM
512x8
REG
CTRL
Bulk-IN
Endpoint
#3
TPRAM
256x8
CTL_IN/INT_IN/BULK_IN
Bulk-OUT
Endpoint
#4
TPRAM
256x8
CTL_OUT/BULK_OUT
SIE
UCOM
Interrupt-IN
Endpoint
#5
BIST
ISO-IN
Endpoint
#1
TPRAM
128x16
ISO-OUT
Endpoint
#2
TPRAM
128x16
USB_TST
ISO-SYNC
Endpoint
#6
Figure 15 USB Function Block Diagram
The USB module supports all transfer types (Control, Bulk In, Bulk Out, Interrupt In, Isochronous In, Isochronous Out and
ISO-SYNC) in USB 1.1 spec and W681308 USB embeds 6 Endpoints include Control Endpoint 0. The default descriptors are
stored in the programmable 512x8 Bit RAM. The SIE module is for handle USB series-interface-engine functions. UCOM
52
Rev1.2
W681308
module is a bridge to communicate SIE and all transfer type modules. Register Control module is for handle MCU read/write
and data signals of W681308 USB registers. Gain Stage residing out off USB module is required for adjusts gain of PCM
data in audio volume control application. USB test module connects many internal signals to test pins for help monitor them
from outside.
The features of USB interface are:
USB Specification version 2.0 Full Speed(FS) 12Mbps compliant
Audio Class Interface and Command support (Volume Control, Mute Control, Sampling Rate selection)
HID Class Interface and Command support (Set/Get Report)
Programmable pull-up resistor to connect/disconnect 1.5Kohm on D+ bus
Support five interfaces and 6 endpoints: Control, Isochronous IN/OUT, Bulk IN/OUT, and Interrupt IN.
Ping-Pong FIFO control for Bulk IN/Bulk OUT transfer to increase data transmission efficiency.
Provide three bytes Isochronous SYNC to synchronize Isochronous OUT with PC audio data stream and improve voice
quality.
19.2.1
Endpoints
The definitions of embedded endpoints are:
Address
Type
Control
ISO
Direction
IN/OUT
IN
maximum Packet Size (Bytes)
Memory Type
64x8 TPRAM
128x16 TPRAM
128x16 TPRAM
128 x 8 TPRAM
128 x 8 TPRAM
64x8 TPRAM
Registers
0
1
64
256
256
128
128
64
2
ISO
OUT
IN
3
Bulk
4
Bulk
OUT
IN
5
Interrupt
ISO
6*
IN
3
Table 12 W681308 USB Endpoint Definitions
NOTE: TPRAM - Dual Ports RAM
53
Rev1.2
W681308
19.2.2
Descriptor RAM
The referenced descriptors are stored in the 512x8 Bit RAM, programmed by MCU. The address mapping and bank
definition of this RAM are shown in 18-2.
Address
Function
Device Descriptor
Size
0x2000~0x2011
18 Bytes
Configuration Descriptor
Interface Descriptor
Endpoint Descriptor
Audio Class Descriptor
HID Descriptor
0x2012~0x217F
366 Bytes
0x2140~0x214F
0x2150~0x215F
0x2160~0x216F
0x2170~0x217F
0x2180~0x21FF
String Descriptor Index 0
String Descriptor Index 1
String Descriptor Index 2
String Descriptor Index 3
Report Descriptor
16 Bytes
16 Bytes
16 Bytes
16 Bytes
128 Bytes
Table 13 USB Descriptor RAM Definitions
54
Rev1.2
W681308
20.
Electrical Characteristics
Absolute Maximum Ratings
20.1
CONDITION
VALUE
UNIT
0C
Junction temperature
150
Storage temperature range
Lead temperature (soldering – 10 seconds)
LQFP-48 Thermal Resistance, typical
Voltage applied to any pin
Input current applied to any digital input pin
ESD (Human Body Model)
VDD - VSS
-65 to +150
0C
300
0C
76
(VSS - 0.3 ) to (VDD + 0.3 )
+/- 10
C/W
V
mA
V
2000
-0.5 to +3.63
-0.5 to + 1.98
0.5
V
VDDL - VSS
V
Power Dissipation
Watt
NOTE: Stresses above the value listed may cause permanent damage to the device. Exposure to absolute maximum ratings
may affect device reliability. Functional operation is not implied at these conditions.
20.2
Recommended Operating Conditions
CONDITION
VALUE
0 to +70
UNIT
0C
Commercial operating temperature
Industrial operating temperature
-40 to +85
+3.13 to +3.47
0C
Supply voltage (VDD) using external regulator
V
Supply voltage (VDDUSB) using internal regulator
and external transistors
+4.4 to + 5.25
0
V
V
Ground voltage (VSS
)
55
Rev1.2
W681308
20.3
DC Characteristics
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VIL
VIH
VT
Input Low Voltage
Input High Voltage
Threshold point
-0.3
2
0.8
3.6
V
V
1.32
1.49
1.24
1.41
1.54
1.29
1.49
1.58
1.34
± 10
± 10
83
V
VT+
VT-
II
Schmitt trigger. Low to High threshold point
Schmitt trigger. high to low threshold point
Input leakage current @VI=3.3V or 0V
Tri-state output leakage current @VO=3.3V or 0V
Pull-up resistor
V
V
µA
µA
K
IOZ
RPU
RPD
VOL
VOH
38
25
54
49
Pull-down resistor
110
0.4
K
Output low voltage @IOL (min)
V
Output high voltage @IOH (min)
2.4
2.2
Low level output current @VOL=0.4V 2 mA
Low level output current @VOL=0.4V 16 mA
High level output current @VOH=2.4V 2 mA
High level output current @VOH=2.4V 16 mA
3.7
29.8
6.4
5.3
mA
mA
mA
mA
IOL
IOH
19.6
3.2
39.0
10.6
77.8
23.1
46.8
20.4
Analog Transmission Characteristics
AVDD=3.13V – 3.47V; VSS=0V; TA=-40°C to +85°C; All ADC tests using Auxiliary input mode @ 0dB gain
TRANSMIT (ADC) RECEIVE (DAC)
PARAMETER
SYMBOL
CONDITION
TYP
UNIT
MIN
MAX
MIN
MAX
ADC (single ended)
DAC (differential)
1.218
2.436
---
---
---
---
---
---
---
---
VPK
VPK
Full Scale Level
Absolute Gain
TXmaX
-3dBFS @ 1020 Hz, AVDD
=3.3V; TA=+25°C;
GABS
0
0
-0.40
+0.40
-0.40
+0.40
dB
dB
Absolute Gain
variation with
Temperature
TA=0°C to TA=+70°C
TA=-40°C to TA=+85°C
-3dBFS
-0.10
-0.20
+0.10
+0.20
-0.10
-0.20
+0.10
+0.20
GABST
AVDD=3.13V – 3.47V; -
3dBFS @ 1020 Hz;
TA=+25°C
Absolute Gain
variation with
Supply Voltage
GABSS
0
-0.10
+0.10
-0.10
+0.10
dB
56
Rev1.2
W681308
20.5
Analog Distortion and Noise Parameters
All ADC tests using Auxiliary input mode @ 0dB gain
20.5.1
8kHz sampling
AVDD=3.13V – 3.47V; VSS=0V; TA=-40°C to +85°C; 8kHz sampling
TRANSMIT (ADC)
RECEIVE (DAC)
PARAMETER
SYMBOL
CONDITION
Idle channel
UNIT
MIN
TYP
94
MAX
MIN
TYP
88
MAX
Signal to Noise Ratio
SNR
THD3
THD8
80
--
--
80
--
--
dB
dB
dB
A-weighted
-3dBFS @ 1020 Hz,
32Ohm speaker load
Total Harmonic Distortion
Total Harmonic Distortion
-77
-77
-67
-67
-69
-77
-70
-67
-60
-55
-3dBFS @ 1020 Hz,
8Ohm speaker load
--
--
-6dBFS @ 1020 Hz,
4Ohm speaker load
Total Harmonic Distortion
Frequency Response
Power Supply Rejection
THD4
Frl
--
-79
3.36
88
--
-65
3.36
85
dB
kHz
dB
-3dB Low pass cut-off
VDDUSB; 35mVrms DC
to 3.4 kHz
PSRRA
70
---
70
---
A-weighted
20.5.2
16kHz sampling
AVDD=3.13V – 3.47V; VSS=0V; TA=-40°C to +85°C; 16kHz sampling
TRANSMIT (ADC)
RECEIVE (DAC)
PARAMETER
SYMBOL
CONDITION
UNIT
MIN
TYP
93
MAX
MIN
TYP
86
MAX
Idle channel
A-weighted
Signal to Noise Ratio
SNR
THD3
THD8
THD4
Frl
80
--
--
80
--
--
dB
dB
-3dBFS @ 1020 Hz,
32Ohm speaker load
Total Harmonic Distortion
Total Harmonic Distortion
Total Harmonic Distortion
Frequency Response
-76
-76
-79
6.73
89
-66
-66
-69
-78
-70
-65
6.73
85
-68
-60
-55
-3dBFS @ 1020 Hz,
8Ohm speaker load
--
--
dB
-6dBFS @ 1020 Hz,
4Ohm speaker load
--
--
dB
-3dB Low pass cut-off
kHz
dB
VDDUSB; 35mVrms
DC to 6.8 kHz
A-weighted
Power Supply Rejection
PSRRA
70
---
70
---
57
Rev1.2
W681308
20.5.3
48kHz sampling
AVDD=3.13V – 3.47V; VSS=0V; TA=-40°C to +85°C; 48kHz sampling
TRANSMIT (ADC)
RECEIVE (DAC)
PARAMETER
SYMBOL
SNR
CONDITION
Idle channel
UNIT
dB
MIN
TYP
MAX
MIN
TYP
MAX
Signal to Noise Ratio
80
--
92
--
80
--
85
--
A-weighted
Total Harmonic
Distortion
-3dBFS @ 1020 Hz,
32Ohm speaker load
THD3
THD8
THD4
Frl
-77
-77
-78
20.2
88
-67
-67
-68
-76
-69
-65
20.2
76
-66
-59
-55
dB
Total Harmonic
Distortion
-3dBFS @ 1020 Hz,
8Ohm speaker load
--
--
dB
Total Harmonic
Distortion
-6dBFS @ 1020 Hz,
4Ohm speaker load
--
--
dB
Frequency Response
-3dB Low pass cut-off
kHz
dB
VDDUSB; 35mVrms
DC to 6.8 kHz
A-weighted
Power Supply
Rejection
PSRRA
70
---
66
---
20.6
Programmable Output Linear Regulator
TA=-40°C to +85°C; Using discrete components per application diagram;
PARAMETER
SYMBOL
VDDUSB
CONDITION
MIN (2)
TYP (1)
MAX (2)
UNIT
Low Power Mode (100mA)
High Power Mode (500mA)
4.4
5
5
5.25
5.25
V
V
Recommended USB Supply
Voltage
4.75
Regulated Supply Voltage
VDD
No Load, Normal Operation
Suspend Mode
3.13
--
3.3
3.47
--
V
Total Suspend Mode
Current
ISP
463
uA
Including USB pull-up and discrete
regulator
Operating Supply Current
Voltage Drop
IVDD
No Load, Normal Operation
VDDUSB =5V, load=500mA
VDDUSB =5V, load=1A
--
--
--
38
--
--
--
mA
V
VDROP0.5
0.006
0.06
Voltage Drop
VDROP1
V
NOTE 1: Typical values: TA = 25°C
NOTE 2: All min/max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all specifications are
100 percent tested
58
Rev1.2
W681308
20.7
USB PHY Electronic Characteristics ( 25°C, DVDD= 3.3V, VDDL =1.8V)
PARAMETER
SYMBOL
CONDITION
MIN.
3.1
TYP.
3.3
MAX.
3.5
UNIT
V
DC Supply Voltage for USB Output Stage
Input Voltage Range for USB_DP/DN
VDD_USB
USB_DP
USB_DN
0
3.5
V
Input High
VIH
VIL
2.0
V
V
Input Low
0.8
Differential Input Sensitivity
Differential Common-mode Range
Single-end Receiver threshold
Output Low
VDI
0.2
0.8
0.8
V
VCM
VSE
VOL
VOH
VCRV
RUP
ZDRV
CIN
---
2.5
2.0
0.3
V
V
V
Output High
2.8
1.3
1.3
8
V
Output signal cross Voltage
Pull-up Resistor
2.0
1.9
19
20
20
20
110
100
2
V
1.61
KΩ
Ω
Driver Output Resistance
Transceiver Capacitance
Driver Rise Time
pF
ns
ns
%
nA
mA
mA
CL = 50pF
Rs=25 Ohms
CEdge=30pF
TR
4
4
8
8
Driver Fall Time
TF
Rise and Fall Time matching
TLRLF
TLRLF = TLR/ TLF
Standby
90
100
VDD_USB Supply Current
IUSB
Input Mode
Output Mode
* (exclude internal pull high resistor)
2
59
Rev1.2
W681308
20.8
USB PLL Electronic Characteristics
PARAMETER
SYMBOL
VPLL
CONDITIONS
MIN.
3.13
TYP.
3.3
12
48
48
56
7
MAX.
3.47
UNIT
V
Operation Voltage
Input Clock Frequency Range
PLL Output Frequency
VCO Frequency
FIN
MHz
MHz
MHz
%
FOUT
FVCO
---
---
Ouput Duty Cycle
46
66
PLL Short-Term Peak To Peak Output Jitter
PLL Lock In Time
TJITTER
TREADY
ps
25
us
60
Rev1.2
W681308
21.
Typical Application Reference Circuit
S1
S6
S2
S3
S4
S5
1
2
5
8
0
3
Mode
Up
HangUp
S7
S8
S9
S10
4
6
Down
USB_5V
S11
S12
S17
S13
S18
S23
S14
S19
S24
S15
7
9
Skype
Left
Down1
Dial
+
C1
S16
S20
S25
*
#
Right
Mute
R1
1M
R2
R3
1uF/10V
PUSHBUTTON
PUSHBUTTON
100K
60K
S21
S22
User
Melody
Up1
Q1
1
MMBT3906
DGND
R4
Q2
VDD_3.3V
PZT2222A
300K
Q3
C2
10nF
R5
MMBT3904
100K
C3
R6
2K
DGND
220uF/10V
UARTT
UARTR
AGND
AGND
AGND
C4
R7
DGND
C5 100nF
C6 100nF
UARTT
UARTR
VREF1
33pF
270
1
2
36
35
34
33
32
31
30
29
28
27
26
25
AGND
AGND
UARTT
VREF1
VREF2
MCP
VREF2
MCP
DY1
12M
R8
UARTR
DGND
XTALO
XTALI
VDDL
DVDD
DN
MIC1
1M
3
DGND
1
2
XTALO
XTALI
MCO
4
1
TP1
MCO
C7
RGND
5
W681308_LQFP
DGND
RGND
AGND
SPP
C8
33pF
6
DGND
AGND
SPP
10nF
7
USB_5V
VDD_3.3V
U1
REC1
SPK1
DN
DP
EARP
8
EARP
AVDD
EARN
SPN
C9
100nF
9
VDD_3.3V
DP
USB Connector
EARN
SPN
10
11
12
DGND
DGND
GPIO3
GPIO0
GPIO3
GPIO0
1
VCC
R9
25
DGND
AGND
2
C10
100nF
D-
3
D+
4
R10 25
GND
C11
C12
51pF
C13
C14
C15
R11
D1
VDD_3.3V
VDD_3.3V
DGND
Shielding
DJP1
51pF
30pF
30pF
AGND
10nF
100
R12
LED
D2
VDD_3.3V
DGND
DGND DGND
DGND DGND
C16
The shielding of the
USB connector can't
connect to any GND.
100
LED
100nF
LCD Module (Serial Interface)
AGND
PCM interface is for
External Audio Device or
USB ATA wtih Pro-X
DGND
AGND
VDD_3.3V
C17
100nF
DGND
Figure 16 W681308 Reference Design Application Circuit
21.1
USB VoIP speaker phone application
The application diagram illustrated that the W681308 is a SOC with very low BOM system design. Externally it supports a
variety interfaces such as keypad, LCM, SLIC, SPI flash/EEPROM, Microphone and speakers directly. External 12M Crystal
as well as a 5V to 3.3V linear regulator is required. Ring tone download and playback is through the same Audio DAC path
with a switch for ringing and speech.
61
Rev1.2
W681308
22.
Package Dimensions
W681308DG is in 48 pin Low-profile Quad Flat Package (LQFP).
In inch
nom
-0.063
In mm
min nom max
Symbol
min
-
max
-
A
A1
A2
b
c
D
E
e
HD
HE
L
-
1.60
0.002 0.004 0.006 0.05 0.10 0.15
0.053 0.055 0.057 1.35 1.40 1.45
0.005 0.008 0.010 0.15 0.20 0.20
0.004 0.005 0.008 0.10 0.15 0.20
0.272 0.276 0.280 6.90 7.00 7.10
0.272 0.276 0.280 6.90 7.00 7.10
0.014 0.020 0.025 0.35 0.50 0.65
0.350 0.354 0.358 8.90 9.00 9.10
0.350 0.354 0.358 8.90 9.00 9.10
0.018 0.024 0.030 0.45 0.60 0.75
L1
Y
θ
-
-
-
0.039
0.004
7’
-
-
0’
-
-
-
1.00
0.10
7’
-
0’
62
Rev1.2
W681308
23.
Ordering Information
Nuvoton Part Number Description
W681308_ _
Package Material:
Pb-free Package
Product Family
G
=
Package Type:
D
=
48-Lead Quad Flat Pack Package (LQFP)
When ordering W681308series devices, please refer to the following part numbers:
Temp
Package
Material
Part Number
Package
Range (oC)
-40 to 85
W681308DG
48-LQFP
Pb-Free
63
Rev1.2
W681308
24. Revision History
VERSION
V0 9
DATE
PAGE
DESCRIPTION
July, 2007
Preliminary Version
V1.0
V1.1
August, 2007
March, 2008
Update Electrical Characteristics
Update Speaker / Earphone attenuation switch
Format of the datasheet changed
Logo update
V1.2
March 2009
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, or for other applications intended to support or sustain life. Furthermore, Nuvoton
products are not intended for applications wherein failure of Nuvoton products could result or lead to a
situation wherein personal injury, death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their own risk
and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales.
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